Jacputer Chip Visualizations
A growing nand2tetris computer, compiled from hand-written HDL into Verilog and interactive browser schematics. Start with the ALU, then descend through the levels until the whole thing bottoms out at primitive NAND gates.
Use this page as the circuit map. It is generated from project Verilog folders such as p1-chip-gates/v/. Each gate has original, level1, level2, and max views.
original keeps immediate subchips boxed. level1 expands one layer. level2 expands two layers. max expands recursively down to Nand leaves.
Flattened views preserve instance names such as mux_0.and_1, but Yosys does not draw nested boxes around each expanded instance. Use the child links to jump into each subchip directly.
